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Ordering number : ENA0367A
Monolithic Digital IC
LB11872V
Overview
For Polygonal Mirror Motors
Scanner Driver IC
The LB11872V is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror in laser printers and similar applications. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11872V can implement motor drive within minimal drive noise due to its use of current linear drive. Note that the LB11872V differs from the LB11872H only in the package.
Functions and features
* Three-phase bipolar current linear drive + midpoint control circuit * PLL speed control circuit * Speed is controlled by an external clock signal. * Supports Hall FG operation. * Built-in output saturation prevention circuit * Phase lock detection output (with masking function) * Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. * On-chip output diodes.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
21407 MS IM 20060614-S00001 / 81006 MH IM 20060213-S00001 No.A0367-1/12
LB11872V
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage Output current Allowable power dissipation 1 Allowable power dissipation 2 Operating temperature Storage temperature Junction temperature Symbol VCC max IO max Pd max1 Pd max2 Topr Tstg Tj max T 500ms Independent IC Mounted on a circuit board *2 Conditions Ratings 30 (*1) 1.5 0.6 1.7 -20 to +80 -55 to +150 150 Unit V A W W C C C
Note *1: This device must be used derated by at least 20% from the rated values. Note *2: Mounted on a specified board: 114.3mmx76.1mmx1.6mm, glass epoxy
Allowable Operating Ranges at Ta = 25C
Parameter Supply voltage range 6.3 V regulator-voltage output current LD pin applied voltage LD pin output current FGS pin applied voltage FGS pin output current Symbol VCC IREG VLD ILD VFG IFG Conditions Ratings 10 to 28 0 to -20 0 to 28 0 to 15 0 to 28 0 to 10 Unit V mA V mA V mA
Electrical Characteristics at Ta = 25C, VCC = VM = 24V
Parameter Supply current 1 Supply current 2 [Output Saturation Voltages VAGC=3.5V] SOURCE(1) SOURCE(2) SINK(1) SINK(2) Output leakage current [6.3 V Regulator-Voltage Output] Output voltage Voltage regulation Load regulation Temperature coefficient [Hall Amplifier Block] Input bias current Differential input voltage range Common-phase input voltage range Input offset voltage [FG Amplifier and Schmitt Block (IN1)] Input amplifier gain Input hysteresis (high to low) Input hysteresis (low to high) Hysteresis width GFG VSHL VSLH VFGL Input conversion 4 5 0 -10 7 12 times mV mV mV IB(HA) VHIN VICM VIOH Differential input: 50mVp-p SIN wave input Differential input: 50mVp-p Design target value* 50 2.0 -20 2 10 (*3) 600 VCC-2.5 20 A mVp-p V mV VREG VREG1 VREG2 VREG3 VCC = 9.5 to 28V Iload = -5 to -20mA Design target value* 5.90 6.25 50 10 0 6.60 100 60 V mV mV mV/C VSAT1-1 VSAT1-2 VSAT2-1 VSAT2-2 IO(LEAK) IO = 0.5A, RF = 0 IO = 1.0A, RF = 0 IO = 0.5A, RF = 0 IO = 1.0A, RF = 0 VCC = 28V 1.7 2.0 0.4 1.0 2.2 2.7 0.9 1.7 100 V V V V A Symbol ICC1 ICC2 Stop mode Start mode Conditions min Ratings typ 5 17 max 7 22 mA mA Unit
*: These value are design guarantee values, and are not tested. Note *3: Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input amplitudes should be held to under 350mVp-p.
Continued on next page.
No.A0367-2/12
LB11872V
Continued from preceding page.
Parameter [Low-Voltage Protection Circuit] Operating voltage Hysteresis width [Thermal Protection Circuit] Thermal shutdown operating temperature Hysteresis width [Current Limiter Operation] Acceleration limit voltage Deceleration limit voltage [Error Amplifier] Input offset voltage Input bias current High-level output voltage Low-level output voltage DC bias level [Phase Comparator Output] High-level output voltage Low-level output voltage Output source current Output sink current [Lock Detection Output] Output saturation voltage Output leakage current [FG Output] Output saturation voltage Output leakage current [Drive Block] Dead zone width Output idling voltage Forward gain 1 Forward gain 2 Reverse gain 1 Reverse gain 2 Acceleration command voltage Deceleration command voltage Forward limiter voltage Reverse limiter voltage [CSD Oscillator Circuit] Oscillation frequency High-level pin voltage Low-level pin voltage External capacitor charge and discharge current Lock detection delay count Clock cutoff protection operating count Lock protection count Initial reset voltage CSDCT3 VRES CSDCT1 CSDCT2 fOSC VCSDH VCSDL ICHG C = 0.022F 4.3 0.75 3 31 4.8 1.15 5 7 2 31 0.60 0.80 V 5.3 1.55 7 Hz V V A VDZ VID GDF+1 GDF+2 GDF-1 GDF-2 VSTA VSTO VL1 VL2 Rf = 22 Rf = 22 0.53 0.32 With phase locked With phase unlocked With phase locked With phase unlocked 0.4 0.8 -0.6 -0.8 5.0 0.5 1.0 -0.5 -1.0 5.6 0.8 0.59 0.37 1.5 0.65 0.42 With phase locked 50 100 300 6 0.6 1.2 -0.4 -1.2 mV mV times times times times V V V V VFG(SAT) IFG(LEAK) IFG = 5mA VFG = 28V 0.15 0.5 10 V A VLD(SAT) ILD(LEAK) ILD = 10mA VLD = 28V 0.15 0.5 10 V A VPDH VPDL IPD+ IPDIOH = -100A IOL = 100A VPD = VREG/2 VPD = VREG/2 1.5 VREG-0.2 VREG-0.1 0.2 0.3 -500 V V A mA VIO(ER) IB(ER) VOH(ER) VOL(ER) VB(ER) IOH = -500A IOL = 500A -5% Design target value* -10 -1 VREG-1.2 VREG-0.9 0.9 1/2VREG 1.2 5% 10 1 mV A V V V VRF1 VRF2 0.53 0.32 0.59 0.37 0.65 0.42 V V TSD TSD Design target value* (junction temperature) Design target value* (junction temperature) 150 180 40 C C VSD VSD 8.4 0.2 8.8 0.4 9.2 0.6 V V Symbol Conditions min Ratings typ max unit
*: These value are design guarantee values, and are not tested.
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No.A0367-3/12
LB11872V
Continued from preceding page.
Parameter [Clock Input Block] External input frequency High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current [S/S Pin] High-level input voltage Low-level input voltage Input open voltage Hysteresis width High-level input current Low-level input current VIH(S/S) VIL(S/S) VIO(S/S) VIS(S/S) IIH(S/S) IIL(S/S) V(S/S) = VREG V(S/S) = 0V -185 2.0 0 2.7 0.1 3.0 0.2 140 -140 VREG 1.0 3.3 0.3 185 V V V V A A fCLK VIH(CLK) VIL(CLK) VIO(CLK) VIS(CLK) IIH(CLK) IIL(CLK) Design target value* V(CLK) = VREG V(CLK) = 0V -185 Design target value* Design target value* 400 2.0 0 2.7 0.1 3.0 0.2 140 -140 10000 VREG 1.0 3.3 0.3 185 Hz V V V V A A Symbol Conditions min Ratings typ max unit
*: These value are design guarantee values, and are not tested.
Package Dimensions
unit : mm (typ) 3285
TOP VIEW 15.0 44 23 Exposed Die-Pad BOTTOM VIEW
5.6 7.6
1 (0.68)
0.65
0.22
22
0.2
SIDE VIEW
(1.5)
1.7max
0.5
SANYO : SSOP44J(275mil)
2.0
Pd max - Ta
Mounted on a specified board: 114.3mmx76.1mmx1.6mm glass epoxy
Allowable Power Dissipation, Pd max - W
1.70 1.5
1.0
0.95
Independent IC
0.60 0.5 0.34
0 -20
0
20
40
60
80
100 ILB01790
Ambient Temperature, Ta -C
No.A0367-4/12
LB11872V
Three-Phase Logic Truth Table
OUT1 to OUT3 (H: Source, L: Sink)
IN1 H H H L L L IN2 L L H H H L IN3 H L L L H H OUT1 L L M H H M OUT2 H M L L M H OUT3 M H H M L L
For IN1 to IN3, "H" means that IN+ is greater than IN-, and "L" means IN- is greater than IN+. For OUT1 to OUT3, "H" means the output is a source, and "L" means that it is a sink.
Pin Assignment
CSD
CLK
S/S
MN
NC
NC
NC
NC
NC
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
FC
PD
LD
24
NC 21 NC
23
LB11872V
1 VREG
2 VCC
3 NC
4 NC
5 NC
6 NC
7 NC
8 SUB
9 RF
10 OUT1
11 OUT2
12 OUT3
13 IN2+
14 IN2-
15 IN1+
16 IN1-
17 IN3+
18 IN3-
19 NC
20 NC
22 NC No.A0367-5/12
Top view
GND
EO
NC
AGC
FG
NC
EI
LB11872V
Equivalent Circuit Block Diagram
CLK
CLK VREG 1 CSD 31 6.3VREG
PD 34 36
EI 37
EO 38 VCC TSD 2 VCC
OSC CLOCK DET PD
LVSD S/S 33 S/S
LD
LD 35
RESET LOCK DET RESTRICT DET LD
PLL
V-AMP 39 9
FC
RF
OCL
FG
FG 32 x5 MN 29
FG FILTER OUTPUT
10 11 12
OUT1 OUT2 OUT3
HALL AMP & MATRIX IN3 IN2 15 16 13 14 17 18 IN1
AGC
28 AGC SUB
8
23 GND
No.A0367-6/12
LB11872V
Pin Functions
Pin No. 1 Symbol VREG Pin Description Stabilized power supply (6.3 V). Insert a capacitor (about 0.1F) between this pin and ground for stabilization. Equivalent Circuit
VCC
22
2 8 9
VCC SUB RF
Power supply SUB pin. Connect this pin to ground. Motor drive outputs. If the output oscillates, insert a capacitor (about 0.1F) between this pin and ground.
VCC
VREG 26 27 28
10 11 12 OUT1 OUT2 OUT3 Output current detection. Insert low-valued resistors (Rf) between these pins and ground. The output current will be limited to the value set by the equation IOUT = VL/RF.
300 25
13 14 15 16 17 18
IN2+ IN2IN1+ IN1IN3+ IN3-
Hall effect sensor signal inputs. These inputs are high when IN+ is greater than INand low when IN- is greater than IN+. The logic high state indicates that VIN+ has a lever higher than VIN-. Insert capacitors between the IN+ and IN- pins to reduce noise. An amplitude of over 50mA p-p and under 350mVp-p is desirable for the Hall input signals. Kickback can occur in the output waveform if the Hall input amplitude is over 350mVp-p.
VCC
300 3 5 7
300 2 4 6
23 28
GND AGC
Ground AGC amplifier frequency characteristics correction. Insert a capacitor (about 0.022F) between this pin and ground.
VREG
300 8
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No.A0367-7/12
LB11872V
Continued from preceding page.
Pin No. 29 31 Symbol MN CSD Monitor pin. This pin should be left open in normal operation. Used for both initial reset pulse generation and as the reference time for constraint protection circuits. Insert a capacitor between this pin and ground. Pin Description Equivalent Circuit
VREG
300 12
32
FG
FG pulse output. This is an open-collector output.
VREG
14
33
S/S
Start/stop control. Low: Start 0V to 1.0V High: Stop 2.0V to VREG This pin goes to the high level when open.
VREG 33k
5k 15 30k
34 CLK Clock input. Low: 0V to 1.0V High: 2.0V to VREG This pin goes to the high level when open.
VREG 33k
5k 16 30k
35 LD Phase locked state detection output. This output goes to the on state when the PLL locked state is detected. This is an open-collector output.
VREG
17
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No.A0367-8/12
LB11872V
Continued from preceding page.
Pin No. 36 Symbol PD Pin Description Phase comparator output (PLL output). This pin output the phase error as a pulse signal with varying duty. The output current increases as the duty becomes smaller. Equivalent Circuit
VREG
18
37
EI
Error amplifier in put pin.
VREG
300 19
38
EO
Error amplifier output pin. The output current increases when this output is high.
VREG
300 20 40k
39 FC Control amplifier frequency correction. Inserting a capacitor (about 5600pF) between this pin and ground will stop closed loop oscillation in the current control system. The output current response characteristics will be degraded if the capacitor is too large.
VREG
21
3 to 7, 19 to 22, 24 to 27, 30, 40 to 44
NC
No connection (NC) pins. These pins may be used for wiring connections.
No.A0367-9/12
LB11872V
Overview of the LB11872V
1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges (low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint control technique to prevent ASO destruction of the output transistors. Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the drive is cut and the motor is left in the free-running state. Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1F) must be inserted between the OUT pins and ground. 3. Hall Input Signals This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the individual phases, discrepancies in the output phase switching timing may occur. An amplitude (differential) of at least 50mVp-p is required in the Hall input signals. However, if the input amplitude exceeds 350mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output. If Hall signal input frequencies in excess of 1 kHz (the frequency in a single Hall input phase) are used, internal IC heating during startup and certain other times (that is, when the output transistors are saturated) may increase. Reducing the number of magnetic poles can be effective in dealing with problem. The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a problem, a capacitor must be inserted across this input. However, since this could result in differences between the signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases. Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only on the low side. 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 6.3V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode. f (Hz) 0.64 / CCSD CCSD (F): The capacitor inserted between the CSD pin and ground. When a capacitor of 0.022F is used, the frequency will be about 29Hz. If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied before the rotor constraint protection time elapses.
No.A0367-10/12
LB11872V
6. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by the capacitor connected to the CSD pin. 30.5x1.57xCCSD (F) If a 0.022F capacitor is used, the protection time will be about 1.05 seconds. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection circuit may not operate normally. 7. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CSD pin and ground. 6.5x1.57xCCSD (F) When a 0.022F capacitor is used, the masking time will be about 225ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. 8. Initial Reset To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero until it reaches 0.63V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good approximation using the following formula. 0.13xCCSD (F) A reset time of over 100s is required. 9. Current Limiter Circuit The current limit value is determined by the resistor Rf inserted between the RF pin and ground. ILIM = VL/Rf VL = 0.6V (typical) (during acceleration) and 0.37V (typical) (during deceleration) 10. Power Supply Stabilization An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. If high-frequency noise is a problem, a ceramic capacitor of about 0.1F must also be inserted in parallel. 11. VREG Stabilization A capacitor of at least 0.1F must be used to stabilize the VREG voltage, which is the control circuit power supply. The capacitor must be connected as close as possible to the pins.
No.A0367-11/12
LB11872V
12. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. 13. Heat sink Area Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity. 14. CSD Pin The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor constraint protection time and the phase lock signal mask time. The following are possible ways of determining the value of this capacitor. (1) If removing chattering from the phase lock state signal is most important: Select a capacitance that can assure an adequate mask time. (2) If startup time is more important than chattering: Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that there are no problems with the clock cutoff protection circuit and initial reset time. Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the uncontrolled state. It is possible to only operate the initial reset function and not operate the rotor constraint protection circuit by inserting a resistor (about 390k) in parallel with the capacitor between the CSD pin and ground. 15. FC Pin The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low, the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow during the current limit time (time before the circuit operates) in states where the output is saturated. (This is because the control response characteristics become worse.) 16. AGC Pin A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must be selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC voltage to reach an essentially stabilized voltage before the initial reset is cleared.
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This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice.
PS No.A0367-12/12

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